ISSN (online) : 2395 - 7549

 
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Performance Estimation of LDPC Code Suing Sum Product Algorithm and Bit Flipping Algorithm


Author(s):

Alpa H. Patel , Shrinathji Institute of Engineering and Technology; Mahesh Kumar Porwal, Shrinathji Institute of Engineering and Technology

Keywords:

LDPC, Sum-Product Algorithm, Bit-Flipping Algorithm, BER (Bit Error Rate)

Abstract:

Low density parity check code is a linear block code. This code approaches the Shannon’s limit and having low decoding complexity. We have taken LDPC (Low Density Parity Check) code with ½ code rate as an error correcting code in digital video stream and studied the performance of LDPC code with BPSK modulation in AWGN (Additive White Gaussian Noise) channel with sum product algorithm and bit flipping algorithm. Finally the plot between bit error rates of the code with respect to SNR has been considered the output performance parameter of proposed methodology. BER are considered for different number of frames and different number of iterations. The performance of the sum product algorithm and bit flip algorithm are also com-pared. All simulation work has been implemented in MATLAB.

Other Details:

Manuscript Id :J4RV2I8008
Published in :Volume : 2, Issue : 8
Publication Date: 01/11/2016
Page(s): 6-11
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