Design and VHDL Implementation of 64-point FFT using Two Structure 8-point FFT/IFFT
Author(s):
Patel Kajalben Ramanbhai , D. N. Patel institute of technology; Prof. S. P. Patil, D. N. Patel institute of technology Shahada, Maharashtra indiaKeywords:
FFT, IP Core and VHDLAbstract:
In this paper, we present a novel fixed-point 32-bit word-width Radix-2 64-point FFT processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal, image processing and FFT processor is a critical block in all multicarrier systems used primarily in the mobile environment. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). FFT blocks are complex to implement and it consumes more resources. So, a efficient technique used here in which FFT is implemented in such a way that it consumes very less resources. This module of 64-point FFT is designed using VHDL programming language. In this work, a pure VHDL design, integrated with some intellectual property (IP) blocks and simulation, synthesis and implementation XILINX ISE 13.2 software is used.
Other Details:
| Manuscript Id | : | J4RV2I11018 |
| Published in | : | Volume : 2, Issue : 11 |
| Publication Date | : | 01/02/2017 |
| Page(s) | : | 25-33 |
